Pietra Calacatta

DSPIC30F6012A

Details

High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• Flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPS operation:
 - DC to 40 MHz external clock input
 - 4 MHz-10 MHz oscillator input with PLL
active (4x, 8x, 16x)
• Up to 41 interrupt sources:
 - 8 user-selectable priority levels
 - 5 external interrupt sources
 - 4 processor traps
DSP Features:
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions are single cycle:
  - Multiply-Accumulate (MAC) operation
• Single-cycle ±16 shift

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